
87158AG
www.idt.com
REV. C JULY 25, 2010
1
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS
÷1, ÷2, ÷4 CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87158 is a high performance 1-to-6 LVPECL-to-
HCSL/LVCMOS ClockGenerator. The ICS87158 has one
differential input (which can accept LVDS, LVPECL, LVHSTL,
SSTL, HCSL), six differential HCSL output pairs and two
complementary LVCMOS/LVTTLoutputs. The six HCSL
output pairs can be individually configured for divide-by-1, 2,
and 4 or high impedance by use of select pins. The two
complementary LVCMOS/LVTTL outputs can be configured
for divide by 2, divide by 4, high impedance, or driven low for
low power operation.
The primary use of the ICS87158 is in Intel E8870 chipsets
that use Intel Pentium 4 processors. The ICS87158 converts
the differential clock from the main system clock into HCSL
clocks used by Intel Pentium 4 processors. However, the
ICS87158 is a highly flexible, general purpose device that
operates up to 600MHz and can be used in any situation where
Differential-to-HCSL translation is required.
FEATURES
Six HCSL outputs
Two LVCMOS/LVTTL outputs
One Differential LVPECL clock input pair
PCLK, nPCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 600MHz (maximum)
Output skew: 100ps (maximum)
Propagation delay: 4ns (maximum)
3.3V operating supply
0°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
GND
VDD
VDD_R
PCLK
nPCLK
GND_R
VDD_M
MREF
nMREF
GND_M
VDD
GND
VDD_L
VDD
GND_L
SEL_T
MULT_0
MULT_1
VDD_L
GND_L
SEL_A
SEL_B
SEL_U
PWR_DWN#
VDD
GND_H
VDD_H
HOST_P1
HOST_N1
GND_H
HOST_P2
HOST_N2
VDD_H
HOST_P3
HOST_N3
GND_H
HOST_P4
HOST_N4
VDD_H
HOST_P5
HOST_N5
GND_H
HOST_P6
HOST_N6
VDD_H
IREF
GND_I
VDD_I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Lead TSSOP
6.1mm x 12.5mm x .92mm body package
G Package
Top View
48-Lead SSOP
7.5mm x 15.9mm x 2.3mm body package
F Package
Top View
V
DD
HOST_P1
HOST_N1
GND_H
V
DD
HOST_P6
HOST_N6
GND_H
V
DD
HOST_P2
HOST_N2
GND_H
V
DD
HOST_P3
HOST_N3
GND_H
V
DD
HOST_P4
HOST_N4
GND_H
V
DD
HOST_P5
HOST_N5
GND_H
V
DD
MREF
nMREF
GND_H
CURRENT
ADJUST
÷1,2,4
MULT_0
MULT_1
IREF
PWR_DWN#
SEL_T
PCLK
nPCLK
SEL_A
SEL_B
SEL_U
DIVIDER
CONTROL
▲
-
+
÷1,2,4
÷2,4